Robust Cyclic ADC Architecture Based on $\beta$-Expansion

In this paper, a robust cyclic ADC architecture with beta-encoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs beta-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain of amplifier in multiplying-DAC (MDAC). Because the power penalty of high-gain wide-band amplifier and the required accuracy of circuit elements for high resolution ADC can be relaxed, the proposed architecture is suitable for deep submicron CMOS technologies beyond 90 nm. We also propose a beta-value estimation algorithm to realize high accuracy ADC based on beta-expansion. The simulation results show the effectiveness of proposed architecture and robustness of beta-encoder.